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  2. VLSI Design Verification And Test
The exhaustive list of topics in VLSI Design Verification And Test in which we provide Help with Homework Assignment and Help with Project is as follows:

  • Design
  • Digital VLSI Design Flow Specification
  • High level Synthesis
  • RTL Design, Logic Optimization
  • Verification and Test Planning
  • Design Representation
  • Hardware Specific Transformations
  • Scheduling, Allocation and Binding
  • Problem Specification: Scheduling
  • Allocation and Binding
  • Basic Scheduling Algorithms (Time constrained and Resource Constrained)
  • Allocation Steps
  • Unit Selection
  • Functional Unit Binding
  • Storage Binding
  • Interconnect Binding
  • Allocation Techniques
  • Clique Partitioning
  • Left-Edge Algorithm
  • Iterative Refinement
  • Logic Optimization and Synthesis
  • Heuristic Minimization of Two-Level Circuits: Espresso
  • Finite State Machine Synthesis
  • Multi-Level Logic Synthesis
  • Multi-Level Minimization
  • Technology Mapping
  • Binary Decision Diagram
  • Construction
  • Reduction rules and Algorithms
  • ROBDDs
  • Operation on BDDs and its Algorithms
  • Representation of Sequential Circuits
  • Temporal Logic
  • Basic Operators
  • Syntax and Semantics of LTL
  • CTL and CLT*
  • Equivalence and Expressive Power
  • Model Checking
  • Verification
  • Specification and Modelling
  • Model Checking Algorithm
  • Symbolic Model Checking
  • Automata and its use in Verification
  • Automata Theoretic Model Checking
  • Practical Examples with SMV
  • Digital Testing
  • Test process and Test economics
  • Functional vs. Structural Testing Defects
  • Errors
  • Faults and Fault Modeling
  • Fault Equivalence
  • Fault Dominance
  • Fault Collapsing
  • Checkpoint Theorem
  • Fault Simulation and Testability Measures
  • Circuit Modeling and Algorithms for Fault Simulation
  • Serial Fault Simulation
  • Parallel Fault Simulation
  • Deductive Fault Simulation
  • Concurrent Fault Simulation
  • Combinational SCOAP Measures
  • Sequential SCOAP Measures
  • Combinational Circuit Test Pattern Generation
  • Automatic Test Pattern Generation (ATPG)
  • ATPG Algebras
  • Standard ATPG Algorithms.
  • D-Calculus and D-Algorithm.
  • Basics of PODEM and FAN.
  • Sequential Circuit Testing and Scan Chains
  • ATPG for Single-Clock Synchronous Circuits.
  • Use of Nine-Valued Logic and Time-Frame Expansion Methods.
  • Complexity of Sequential ATPG.
  • Scan Chain based Sequential Circuit Testing.
  • Scan Cell Design.
  • Design variations of Scan Chains.
  • Sequential Testing based on Scan Chains.
  • Overheads of Scan Design.
  • Partial-Scan Design.
  • Built in Self test (BIST)
  • BIST architecture BIST Test Pattern Generation.
  • Response Compaction.
  • Response Analysis.
  • Memory BIST.
  • March Test.
  • BIST with MISR.
  • Neighborhood Pattern Sensitive Fault Test.
  • Transparent Memory BIST.